Lesson 12: Printed Circuit Board Layout with Circuit Mason

This section is optional, and covers the actual construction of a circuit board. Circuit Mason uses a powerful layout generation tool that simplifies the design cycle considerably. Mason has two output options that are useful for two different scenarios. One scenario is if the schematic represents the entire design, and the other scenario is if the schematic represents only a part of a larger circuit. Both of these cases will be explored, and details will be provided on how to fabricate a board for a senior design project.

The first section will focus on describing important considerations for creating a design for the auto-layout tool. In the second section we will show how to generate a decal for use in a larger design. In the third section we will design and optimize a simple filter and bring that into layout. A fourth section will describe how these designs can be exported to Gerbers for fabrication.

Section 1: Amplifier Circuit

The first design we will explore will require no optimization; it will go through the steps of using Mason to create a layout. The output of Mason can be imported directly into the PADS Layout program, which can be run in a demo mode for these circuits. Because using PADS in general is beyond the scope of this lesson, please download the starter_board.pcb file from https://sites.google.com/site/circuitmason/home/test_cabinet. We will use this file as a starting location for all of the designs in this lesson.

Step 1: Layout Design Considerations

Rather than build the design from scratch, download the hmc478_layout.dsn file from https://sites.google.com/site/circuitmason/home/test_cabinet. We will note several important features of this designs.

(Smart) Footprints

Every component has a package type defined, and Mason deals with two types of packages. All of the components in this design are “smart footprints” (or “smart decals”), meaning Mason knows how to automatically place these components in the layout. To be a smart footprint, not only must the copper be defined, but the connection point must also be defined as well. Where the connection point exists depends on the model: for a microstrip, the connection point should be at the end of the microstrip, because that's the reference plane of the model; for a resistor, the connection point might be in the middle of the pad, because that's the reference plane of the model. The model might not include the actual pad the component is soldered on.

Figure 12.1 and Figure 12.2 show the schematic and layout view of the input of this design. The simulation port is ignored by the layout tool. The Thru SMA connector has a microstrip running to an 0402 capacitor, and another microstrip line goes off to the right. The process is fairly simple... the challenge is getting the details right.

Figure 12.1: Schematic view of the input of the amplifier

Figure 12.2: Layout view of the input of the amplifier

The Connector

Simulation: The connector is treated as a two port device in the simulation. From a simulation perspective, Mason treats this connector as an added inductance. The actual inductance varies from model to model, but inexpensive SMA connectors tend to range from 0.5nH to 3nH. You may need to tweak your model to get measurement agreement.

Schematic: Note that the connector's schematic symbol has Port defined on one of the pins. The Port text should be on the side that connects to the Port (_Port1 in this example). From a Layout perspective, the component is a five terminal device- four terminals are grounded and one is for the signal. In the simulation, we have a signal input and a signal output. Because we have only defined the signal pin connection, we will have to connect the ground connections manually in the layout as a later step. It's a minor inconvenience caused by the mismatch between how the code treats the model and how the code treats the layout.

Layout: Whereas most layout packages have a number of built-in “dumb” footprints for parts, this component's footprint (decal) is described in a special Mason file. The microstrip line will launch from the center point of the connector. It is important to make sure that the microstrip line clears the connector. For example, if the microstrip line is not long enough, then C1 (the inline capacitor) could be under the surface mount connector... which would be a layout error. Each surface mount part should have some amount of clearance between every other surface mount part; as a rule of thumb use 50 mils between parts.

The Microstrip Lines

Simulation: The microstrip lines are simulated using an algebraic approximation which have an accuracy of a few percent.

Schematic: This is a two port device in both the simulation and the layout, therefore the part will be connected properly.

Layout: The microstrip line is generated based on the last optimization value. When optimizing the microstrip parameters, update the schematic (and save, if desired) to see what values were used to actually generate the layout.

The Capacitor

Simulation: Mason includes both an ideal capacitor model and the ability to use measured data (typically provided by vendors). This capacitor used measured data. The schematic part has 34 discrete values packaged under one component, and the integer “value” determines which of the files are used for the simulation.

Schematic: The descriptive value (here, 100pF) is updated when the simulation is run and the schematic is updated (if you change the value to 33, run Mason, and update the schematic, the descriptive value will update to 82pF).

Layout: Most Layout tools will have built-in decals (footprints) for the common types of capacitors. For this component, we are using a smart footprint: “file: lumped_elements\0603.xml”. A dumb decal would be to use a package of “0603”, but Mason will not be able to stitch the layout as effectively. The smart footprints that are available are generally located under the “lumped_elements” directory; to change to a smart footprint (or to a dumb footprint) you may need to update your “Package” definition (Figure 12.3).

Figure 12.3: This inductor uses a Smart Footprint; replace "file: lumped_elements\0805.xml" with simple "0603" (no "file:") to use a dumb decal

The Amplifier (HMC478)

Simulation: Amplifiers are generally two port devices, as far as simulation goes. The actual amplifier is at least a three terminal device (at least one ground terminal is needed). In Figure 12.4, we see that this amplifier has an input port, an output port, and two pins that are grounded. Unlike the connector, however, we do not need to spoof two ports on a single pin (the connector model is an inductor between two ports, but the connector only has one physical connection point for the signal on the board). We just need to identify how to map the schematic pins to the simulation ports: we use the “Nodes” parameter (Figure 12.5) to set that. From the data sheet, we see that Pin 1 goes to Port 1, Pin 2 is grounded (not part of our simulation's S-Parameters), Pin 3 goes to Port 2, and Pin 4 is grounded (not part of our simulation's S-Parameters). The “Nodes” parameter uses “0” to mean “not part of the simulation, and so our Nodes are described as “1 0 2 0” (pin 1→ Port 1, pin 2 → not used, pin 3 → Port 2, pin 4 → not used).

Figure 12.4: Amplifier schematic symbol

Figure 12.5: The "Nodes" parameter defines how the schematic pins map to the simulation ports

Schematic: The schematic here uses the “Power Tools Option” located near the wire tool to create a ground. Mason's layout tool treats this type of ground differently than the RF Ground under the “mason” library. The “Power Tools” ground is both an RF ground and a chassis ground. This is what we normally consider as ground. But consider the 5V voltage supply (Figure 12.6): from a simulation perspective this is an RF ground, but from a layout perspective this is a different node. That is why we have two different grounding options in Mason.

Figure 12.6: RF ground applied to a voltage supply

The bias line

Simulation: The bias network (Figure 12.7 and Figure 12.8) includes a complete set of microstrip lines to space out a series inductor (L1) which acts as an RF choke, and a shunt capacitor (C3) which helps prevent RF from reaching the 5V supply line. The inductor is a high impedance at RF, making it hard for the RF to get to the 5V line. The capacitor is an RF short, reflecting the RF away from the 5V supply line.

Schematic : The capacitor is grounded with the Power Tools ground; this is a true ground from a layout perspective.

Layout: The microstrip lines (especially the T-Junction) are used to make sure the circuit is properly laid out with some distance between the components. This component uses a smart footprint, where the connection point is along the center-line of the pad. Some amount of microstrip is needed to provide distance between neighboring capacitors and inductors.

Figure 12.7: Schematic of the bias network

Figure 12.8: Layout of the bias network

The Flags

Schematic: We simply note that one of the flags is: “PADS-ASCII = hmc478_test.asc”; this tells Mason to generate the PADS asc file used for layout.

Step 2: Running the Simulation

The simulation should be run (the “M” button), and the schematic should be updated and saved (“U” and “S” respectively). Plot the results (the “P” button).

Questions:

12.1.1: Plot the input and output impedance of the amplifier. How does this compare with how we have generally defined a good impedance (below -20dB)?

12.1.2: Plot the gain and isolation (S_2_1 and S_1_2 respectively) of the amplifier. The circuits we have been dealing with have been reciprocal (S_2_1 is equal to S_1_2). Is the amplifier reciprocal? Comment on the results.

Step 3: Importing the Design

Mentor Graphic's schematic and layout suite, PADS, can be downloaded and run in demo mode for free. The demonstration mode is suitable for simple circuits- the restrictions arise when larger designs are created. Once the package is installed, open up the “starter_board.pcb” file (which is a simpler starting point for simulation), which can be found at: https://sites.google.com/site/circuitmason/home/test_cabinet.

Use File → Import, and find the file “hmc478_test.asc”.

Figure 12.9: Imported design into starter_board.pcb

Step 4: Centering the components on the board

Hit escape (to make sure nothing is selected), right click on the layout, and choose “Select components”. This makes sure we only select components when we grab parts in order to center.

Left click and drag to select the component just imported. Do not select J1 and CBYPASS1. You should see the following (where black and white have been flipped):

Figure 12.10: Imported components have been selected (black and white have been inverted)

Use Ctrl-E to make the parts movable, move the parts to roughly the middle of the board, and left click again.

Figure 12.11: After the parts have been moved

Step 5: Making silkscreen labels for the parts

Hit escape (to make sure nothing is selected), right click and choose “Select Component”.

Left click on one of the connectors to select (doesn't matter which, we will be doing this for both), right click to pull up the contextual menu, and select “Properties...”. Click on the Labels tab, and click on the button in the tab (has a U1, 7400 on the button), and click “OK” on the window that popped up. Repeat this step for the other connector, plus the capacitors, inductors, and amplifier (just the placed parts, not the microstrip).

Hit escape (to make sure nothing is selected), right click and choose “Select Documentation”. Click on each new label, use Ctrl-E to make the label moveable, and left click on the new location. You can also use Ctrl-R to rotate the label.

Figure 12.12: ECO Toolbar button is two circles and a 45 degree line

Figure 12.13: Layout with added labels

Step 6: Connecting the 5V Line

Hit escape, right click on the layout, and “Select Anything”. There is a line connecting the microstrip from CBYPASS1 to the microstrip leading to C3. Double click on the right pad of CBYPASS1 and a routing trace will appear. Bring this line down to the microstrip (you will see a thin white line indicating where you should go) and left click on the end of the microstrip (you should see a target reticle when you are on the correct spot).

Figure 12.14: 5V Line connected

Step 7: Ground Connections

Because the connectors were not properly grounded, we will need to adjust the nets in the schematic. Click on the ECO Toolbar (“OK” the pop-up), and click the “Add connection” button (which looks remarkably like the ECO Toolbar button).

Figure 12.15: The "Add connection" button is on the far left of the ECO toolbar and looks identical

Left click on the left pad of CBYPASS1 (the ground side), and you should see a white line following away from that pad (try again if you don't). Left click in turn the four outer pads of both SMA1 and SMA2. You should see something like Figure 12.16, then hit escape to stop adding connections.

Figure 12.16: Four outer pins of both connectors added to the ground net

Step 8: Adding Ground Vias and traces

This is a simplified way of grounding the parts; there are better grounding practices than what we are doing here, but this will work well enough for this introduction.

Double click on the big pad of U1 (one of the ground pins) to bring up a routing trace, and click on the smaller center pin just to the left (you will get a target reticle when you're on the right spot).

Not a repeated step: Double click on the big pad of U1 (one of the ground pins) to bring up a routing trace, move around 250 mils to the right, and right click and select “End Via Mode” → “End Via”. Right click again and select “End”. This should drop a via.

If the 5V trace we added previously seems too close to the ground via we just created, left click on the trace, hit Ctrl-E to move, and shift the line 100mils or so to the right.

Double click on the smaller center pad of U1 (one of the ground pins) to bring up a routing trace, move around 250 mils to the left, right click and select “End”. This should drop a via.

For SMA2, the surface mount connector, for each pad:

1. left click on the ground pads
2. right click and select “Add via at SMD”

For SMA1, the through hole connector, for each pad:

1. left click on the ground pad
2. right click and select “Properties”
3. fill in the “Plane Thermal” check box

For the unconnected end of the microstrip line of C3, double click on the end of the line to bring up a routing trace, move around 50 mils down, right click and select “End”. This should drop a via.

The layout should now look as Figure 12.17 below.

Figure 12.17: Layout with ground vias

Step 9: Flooding the ground planes

Select from the top menu: Tools → Pour Manager... → the Plane Connect tab → Select All → Start.

Figure 12.18: Flooded artwork

Step 10: Generate CAMS

First, we need to make sure our gerbers will be properly generated. File → CAM... to bring up the CAM window. Double click on “copper_layer_1”, click on “Device Setup...”, “Advanced...”, and make sure “Use fill mode (G36, G37) is checked”- we need this check marked!

Next, left click on “board_outline”, hold down on the shift key, and click on “silkscreen_layer_1”. Click the Run button, and the CAM files will be generated in your PADS CAM directory, which by default is “C:\PADS_Projects\CAM\default”; if you have chosen a different location for the PADS_Projects folder, you will need to find the CAM directory.

A number of errors will pop up, these can be ignored for now.

Delete the *.rep files and the NC_drill.lst (we don't need them).

Put the following information in a readme.txt file in that directory:

Board stack-up:

Layer 1: min 0.5oz copper (plate to thicker)

10-mil RO4350

Layer 2: min 0.5oz copper (plate to thicker)

Copper layers:

Layer 1: copper_layer_1.pho

Layer 2: copper_layer_2.pho

Silkscreen Layers:

Layer 1: silkscreen_layer_1.pho

Solder layers (negative mask):

Layer 1: solder_layer_1.pho

Layer 2: solder_layer_2.pho

Drill file (NC Drill):

Plated through holes: NC_drill.drl

You should now be able to zip up all of these files (including the readme file) and send them to a board house for fabrication.

Step 11: What we could do better

The amplifier and SMA2 are not especially well grounded. Smaller vias and more of them would do a better job, for RF performance for both of them. This would also lower the risk of the pads of SMA2 pulling off of the board and would improve the heat dissipation for U1.

Section 2: Wilkinson Decal (Advanced and Optional)

Mason has two PADS ASCII file outputs; the simple “.asc” file is always valid. Each device in the schematic is represented as a separate (placed) part in the ASCII file. This is a robust way to output a complete design, since both smart and dumb footprints can be used and the nets will be properly mapped. While this ASCII file can be imported into an existing design, linking to DxDesigner (for example) will delete all of the components imported from Mason.

The second “.asccombined.asc” file is an attempt to stitch together all of the individual devices into a single decal. For some larger projects, it may be desirable to use a design from Mason as a component in a larger schematic, for example design the RF section in Circuit Mason but use a different schematic tool (e.g., DxDesigner) for the overall design. This flow works well for a certain class of circuits- microstrip filters, combiners, and couples, for example.

For any design where either the RF section or the rest of the design will be modified often (for example, reassigning digital lines to simplify the layout, the combined technique is a far easier flow.

To avoid the steps of building the file, download the single_wilkinson.dsn file at: https://sites.google.com/site/circuitmason/home/test_cabinet.

Step 1: Considering the Caveats

The devices must all be properly constructed smart footprints (like microstrip lines) which all connect to each other.

1. The “sma_142-0701-201.xml” connector is a smart footprint, but because of the inline trick this part can't be used in the combined ASCII file.
2. Dumb components are ignored- if the dumb component is and series and it breaks the continuity of the layout, that can be a problem. If the dumb component is in parallel and there is another path, that can work. The resistor is a Wilkinson is in parallel and not a problem.

Step 2: Running the Simulation

The simulation should be run (the “M” button), and the schematic should be updated and saved (“U” and “S” respectively). Plot the results (the “P” button).

Questions:

12.2.1: In a previous lesson, we discussed how the input match can work over a wider bandwidth than the isolation and the output match. This is because the input match can make use of the TL1 device. How does the bandwidth of the input match (S_1_1) compare with the isolation (S_2_3) and the output match (S_2_2)? Comment on the results.

Step 3: Importing the Design

Use File → Import, and find the file “single_wilkinson.asccombined.asc”.

Figure 12.19: Imported Wilkinson

Note the resistor, as a dumb 0402 part, is not included. This is a feature: if the auto-layout tool tried to place a smart footprint version of the 0402 part, then the locations of some of the devices would be defined twice. The geometry is over-specified.

Also, by not including the resistor in the footprint, the resistor must included in the other schematic tool (the one which will have a symbol which uses this decal as a package). This means the resistor must be defined as a separate part, which means the resistor will show up in the Bill of Materials of the master schematic... which is a good thing.

The symbol in the other schematic will have five terminals. Three are the input/output ports of the Wilkinson, and two are the terminals that the resistor will connect to. This way, the 0402 part will have the nets defined to attach to the proper place in the decal.

Step 4: Centering the components on the board

Hit escape (to make sure nothing is selected), right click on the layout, and choose “Select components”. This makes sure we only select components when we grab parts in order to center.

Left click and drag to select the component just imported. Do not select J1 and CBYPASS1. You should see the following (where black and white have been flipped):

Figure 12.20: Imported component has been selected and centered

Use Ctrl-E to make the parts movable, move the parts to roughly the middle of the board, and left click again.

Step 5: Examining the Terminals

Hit escape (to make sure nothing is selected), right click on the layout, and choose “Select Anything”.

Figure 12.21: Wilkinson with Terminal 1 selected (white and black have been inverted)

This circuit has 26 potential terminals: twelve microstrip lines where each line has at least two terminals, the T-junctions have three terminals. Mason needs to map these microstrip lines into a five terminal decal. It does this by noting which terminals go to a port (the three inputs) and which terminals go to a dumb footprint (and therefore needs terminals to make the connection to an external part). Of the 26 terminals, 21 do not go to an external device, and therefore these copper sections are all mapped to terminal 1 of the combined decal.

In Figure 12.21, terminal 1 is selected (the black shape). The outputs and the resistor connection points are not selected- these are separate terminals.

Step 5: Examining the Component

Hit escape (to make sure nothing is selected), right click on the layout, and choose “Select Component”. Select the Wilkinson, right click and select “Edit Decal”. The actual terminal numbering can be seen (Figure 12.22). The input is terminal 1, the outputs are terminals 4 and 5, and the resistor will go across terminals 2 and 3. This numbering is critical information when constructing a symbol in the schematic tool- these are the port pins in the schematic.

In the Decal Editor, we can save the decal with File → Save Decal As, and choose a library and a name (use a descriptive name, the default is not very useful). When this decal is saved, it can be used by DxDesigner (or other tools using PADS).

File → Exit Decal Editor to get back to the layout (click “cancel” for the pop-up).

Figure 12.22: Decal with the terminals numbered

Step 6: Next Steps

The decal has been brought into the PADS library and the next step is creation of the schematic symbol. Care must be taken to make sure the schematic symbol correctly maps the terminals, as shown in Figure 12.22. If the RF design is updated, this process can be repeated to update the layout.

Section 3: Filter Design

Filters can be constructed from many different types of components: discrete inductors, capacitors, or microstrip lines of varying widths and lengths. The particular filter in this section uses coupled microstrip lines. The design created in this lab is interesting because it requires a minimum of soldered parts.

Step 1: Design

The first step in the design process is to choose the filter parameters. The most important parameters to start with are the band of operation, the input impedance, and the filter order. For this example, the bandwidth will be 100MHz, the center frequency will be 2.45GHz, the input impedance will be 50Ω, and we will use a third order filter.

The fractional bandwidth needed for the design is defined by:

Equation 12.1

The order of the filter controls the roll-off of the response. We can use filter tables to determine the impedances of the filter elements. Filter tables list the normalized impedances for all sorts of filter types, such as:

- - 1. Butterworth: maximally flat in the pass band
    2. Cheybshev: equal ripple in the pass band
    3. Linear phase: maximally flat group delay

A set of example data for two types of third order filters are presented in the table below.

Table 12.1: Prototype values for the filter

Unlike lumped element filters, where the number of elements corresponds to the order of the filter, the coupled line filter has an order one less than the number of elements- for a third order filter we need four coupled lines. The calculations for a Butterworth filter will be performed, and it will be left as an exercise to simulate the Chebyshev filter.

The equations for the filter design are listed below. The first and last element use different equations than all of the middle elements. Because the filter is symmetric (same impedances on both sides), we expect the filter elements to have symmetric values: otherwise we probably made a mistake.

Equation 12.2

Equation 12.3

Equation 12.4

Equation 12.5

Equation 12.6

Table 12.2: Design impedances for the filter

Step 2: Design of the Coupled Lines

The next step of the design process is to determine the physical dimensions of the coupled lines based on the desired even and odd impedances. To calculate this, we will use the transmission line calculator included in the Circuit Mason distribution, PrimCalc.

PrimCalc can be used to analyze or synthesize transmission lines. Run PrimCalc and load the file (in the microstrip folder) called “medgecoupled.xml”. For a common substrate (RO4350) the arguments should be:

- Frequency of 2.45 GHz
- Permittivity of 3.66
- Dielectric thickness of 30 mil
- Width of 10 mil (we'll be changing this soon)
- Thickness of 0.7 mil
- Gap of 4 mil (we'll be changing this soon)
- Length of 19 mm (we'll be changing this soon)
- Ceiling height of 1m
- Conductivity of 4e6
- Loss tangent of 0.002

Run Calc and you should see the results below:

Figure 12.23: PrimCalc analysis of the coupled lines

To synthesize the transmission line, check the boxes next to the “width” and “gap” arguments, and check the boxes next to the “Z0even_fn” and “Z0odd_fn” properties. This defines which properties should stay fixed, and which arguments should be free. Fill in the first set of even and odd impedances, and hit the “Calc” button.

Figure 12.24: PrimCalc synthesis of the coupled lines

Solving for the widths and gaps, the four lines have the following dimensions:

We can also load the “mline” model in PrimCalc and see that a 50Ω impedance on the same substrate is 64.6 mils wide.

We have not yet optimized for the length of the microstrip lines; we will do that during simulation.

Step 3: Simulation

The next step is simulation of the coupled microstrip filter. We will need a frequency block (2.3 – 2.5 GHz) and a flag block (with the PADS-ASCII output defined), both from the “mason” library. We will need a microstrip “properties” block, available from the “mason_microstrip” library. We will also want a variable block, which can be found in the “mason” library.

Figure 12.25: Control blocks for the Mason simulation

The simulation will include some connectors (“mason_connectors”), microstrip lines and microstrip edge coupled lines (“mason_microstrip”), as well as the ports. Make sure that the “Port” side of the connector is facing towards the port. Note that the first and last microstrip edge coupled lines use equal widths and gaps, and the second and third microstrip edge coupled lines use equal dimensions.

Figure 12.26: Design of the coupled line filter

Figure 12.27: Plot of the coupled line filter's response

Simulation will show the filter is close, but not quite right. The design is frequency shifted: the design was for a filter 100MHz centered centered at 2.45 GHz and is centered around 2.34 GHz. To fix this, we need to adjust the line length (we approximated 19mm earlier). We can use the optimizer, or we can calculate that the frequency needs to be shifted by 4.7% (2.45/2.34). To make the filter work at a higher frequency, the line length needs to be decreased, so the line needs to be 19mm * 2.34/2.45 = 18.15 mm.

Figure 12.28: Corrected line length for the coupled line filter

The second problem with the design is the drop out between 2.4 and 2.45 GHz. This is caused by the inductance modeled in the connectors. The truth is we aren't sure what the inductance is in the connectors until we measure them. For example, if we assume the inductance is 1nH by changing the inductance in SMA1 and SMA2 from 2.6nH to 1nH, we get the following response.

Figure 12.29: Assuming less inductance in the connectors

We will back out the inductance in the connectors when we fabricate the design.

Step 4: Layout

Because using PADS in general is beyond the scope of this lesson, please download the starter_board2.pcb file from https://sites.google.com/site/circuitmason/home/test_cabinet. We will use this file as a starting location for all of the designs in this lesson.

1. File → Import the PADS-ASCII file (optimizing_filter.asc)

Figure 12.30: Coupled line filter imported into starter_board2.pcb

2. Hit escape, right click and select “Select Components”. Select the RF components and move them to the left (using Ctrl-E) onto the board.

Figure 12.31: Coupled line with the components shifted onto the board

3. Because the connectors were not properly grounded, we will need to adjust the nets in the schematic.

1. Click on the ECO Toolbar, which looks like two circles connected by a 45° line (“OK” the pop-up), and click the “Add connection” button (which looks remarkably like the ECO Toolbar button).

Figure 12.32: ECO Toolbar

2. Left click on the left pad of CBYPASS1 (the ground side), and you should see a white line following away from that pad (try again if you don't). Left click in turn the four outer pads of both SMA1 and SMA2.

Figure 12.33: Coupled lines with the nets properly connected

3. Next the CAM files need to be generated.

1. File → CAM... to bring up the CAM window. Double click on “copper_layer_1”, click on “Device Setup...”, “Advanced...”, and make sure “Use fill mode (G36, G37) is checked”- we need this check marked!

2. Next, left click on “board_outline”, hold down on the shift key, and click on “silkscreen_layer_1”. Click the Run button, and the CAM files will be generated in your PADS CAM directory, which by default is “C:\PADS_Projects\CAM\default”; if you have chosen a different location for the PADS_Projects folder, you will need to find the CAM directory.

3. Delete the *.rep files and the NC_drill.lst (we don't need them).

4. Put the following information in a readme.txt file in that directory:

Board stack-up: